1. Technical Field
The present invention relates to a method and structure for reducing power dissipation in microelectronic circuits, and more particularly for reducing coupled capacitance power dissipation.
2. Related Art
Reducing power dissipation is becoming increasingly difficult in Very Large Scale Integration (VLSI) design, due to constraints on battery life on ‘low-end’ consumer electronics and thermal dissipation constraints on ‘high-end’ servers. As microelectronic technology has been scaled downward, several device characteristics have compounded the problems of designing for lower power, including larger transistor counts, increased device leakage, higher switching speeds, and increased coupling capacitance. Thus, there is a need to reduce power dissipation in microelectronic circuits notwithstanding the device characteristics.